This data hazard can be detected quite easily when the
program's machine code is written by the compiler. The original
Stanford RISC machine relied on the compiler to add the NOP
instructions in this case, rather than having the circuitry to
detect and (more taxingly) stall the first two pipeline stages.
Hence the name MIPS: Microprocessor without Interlocked
Pipeline Stages. It turned out that the extra NOP instructions
added by the compiler expanded the program binaries enough that
the instruction cache hit rate was reduced. The stall hardware,
although expensive, was put back into later designs to improve
instruction cache hit rate, at which point the acronym no
longer made sense.